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a
FEATURES Low Cost Single (AD8061), Dual (AD8062) Single with Disable (AD8063) Rail-to-Rail Output Swing 6 mV V OS High Speed 300 MHz, -3 dB Bandwidth (G = 1) 800 V/ s Slew Rate 8.5 nV/Hz @ 5 V 35 ns Settling Time to 0.1% with 1 V Step Operates on 2.7 V to 8 V Supplies Input Voltage Range = -0.2 V to +3.2 V with VS = 5 Excellent Video Specs (RL = 150 , G = 2) Gain Flatness 0.1 dB to 30 MHz 0.01% Differential Gain Error 0.04 Differential Phase Error 35 ns Overload Recovery Low Power 6.8 mA/Amplifier Typical Supply Current AD8063 400 A when Disabled Small Packaging AD8061 Available in SOIC-8 and SOT-23-5 AD8062 Available in SOIC-8 and SOIC AD8063 Available in SOIC-8 and SOT-23-6 APPLICATIONS Imaging Photodiode Preamp Professional Video and Cameras Hand Sets DVD/CD Base Stations Filters A-to-D Driver PRODUCT DESCRIPTION
NC 1 -IN 2 +IN 3 -VS 4
Low-Cost, 300 MHz Rail-to-Rail Amplifiers AD8061/AD8062/AD8063
CONNECTION DIAGRAMS (Top Views) SOIC-8 (R) SOT-23-6 (RT)
AD8061/ AD8063
8 7 6
DISABLE
(AD8063 ONLY)
VOUT 1 -VS 2 +IN 3
AD8063
6 +VS 5
+VS VOUT NC
DISABLE -IN
(Not to Scale)
5
4
(Not to Scale)
NC = NO CONNECT
SOIC-8 (R) and SOIC (RM)
AD8062
1 2 3 4 (Not to Scale) 8 7 6 5 +VS VOUT2 -IN2 +IN2
SOT-23-5 (RT)
AD8061
VOUT 1 -VS 2 +IN 3 (Not to Scale)
4 5
VOUT1 -IN1 +IN1 -VS
+VS
-IN
The AD8061, AD8062, and AD8063 offer a typical low power of 6.8 mA/amplifier, while being capable of delivering up to 50 mA of load current. The AD8063 has a power-down disable feature that reduces the supply current to 400 A. These features make the AD8063 ideal for portable and battery-powered applications where size and power are critical.
3 RF = 50 0
NORMALIZED GAIN - dB
The AD8061, AD8062, and AD8063 are rail-to-rail output voltage feedback amplifiers offering ease of use and low cost. They have bandwidth and slew rate typically found in current feedback amplifiers. All have a wide input common-mode voltage range and output voltage swing, making them easy to use on single supplies as low as 2.7 V. Despite being low cost, the AD8061, AD8062, and AD8063 provide excellent overall performance. For video applications their differential gain and phase errors are 0.01% and 0.04 into a 150 load, along with 0.1 dB flatness out to 30 MHz. Additionally, they offer wide bandwidth to 300 MHz along with 800 V/s slew rate. REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
-3
VO = 0.2V p-p RL = 1k VBIAS = 1V RF
RF = 0
-6 OUT IN 50 -9 VBIAS RL
-12 1 10 100 FREQUENCY - MHz 1000
Figure 1. Small Signal Response, RF = 0 , 50
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD8061/AD8062/AD8063-SPECIFICATIONS unless otherwise noted)
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise Differential Gain Error (NTSC) Differential Phase Error (NTSC) Third Order Intercept SFDR DC PERFORMANCE Input Offset Voltage TMIN to TMAX Input Offset Voltage Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing--Load Resistance Is Terminated at Midsupply Output Current Capacitive Load Drive, VOUT = 0.8 V POWER-DOWN DISABLE Turn-On Time Turn-Off Time DISABLE Voltage--Off DISABLE Voltage--On POWER SUPPLY Operating Range Quiescent Current per Amplifier Supply Current when Disabled (AD8063 Only) Power Supply Rejection Ratio
Specifications subject to change without notice.
(TA = 25 C, VS = 5 V, RL = 1 k , VO = 1 V,
Min 150 60 Typ 320 115 280 30 650 500 35 -77 -50 -90 8.5 1.2 0.01 0.04 28 62 1 2 3.5 3.5 4 0.3 70 90 13 1 -0.2 to +3.2 80 0.1 to 4.5 0.1 to 4.9 50 25 300 40 300 2.8 3.2 2.7 5 6.8 0.4 80 8 9.5 4.75 4.85 6 6 9 9 4.5 Max Unit MHz MHz MHz MHz V/s V/s ns dBc dBc dBc nV/Hz pA/Hz % Degree dBc dB mV mV V/C A A A dB dB M pF V dB V V mA pF pF ns ns V V V mA mA dB
Conditions G = 1, VO = 0.2 V p-p G = -1, +2, VO = 0.2 V p-p G = 1, VO = 1 V p-p G = 1, VO = 0.2 V p-p G = 1, VO = 2 V Step, RL = 2 k G = 2, VO = 2 V Step, RL = 2 k G = 2, VO = 2 V Step fC = 5 MHz, VO = 2 V p-p, RL = 1 k fC = 20 MHz, VO = 2 V p-p, RL = 1 k f = 5 MHz, G = 2, AD8062 f = 100 kHz f = 100 kHz G = 2, RL = 150 G = 2, RL = 150 f = 10 MHz f = 5 MHz
500 300
VO = 0.5 V to 4.5 V, RL = 150 VO = 0.5 V to 4.5 V, RL = 2 k
68 74
VCM = -0.2 V to +3.2 V RL = 150 RL = 2 k VO = 0.5 V to 4.5 V 30% Overshoot: G = 1, RS = 0 G = 2, RS = 4.7
62 0.3 0.25 25
VS = 2.7 V to 5 V
72
-2-
REV. C
SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1%
AD8061/AD8062/AD8063
(TA = 25 C, VS = 3 V, RL = 1 k , VO = 1 V, unless otherwise noted)
Conditions G = 1, VO = 0.2 V p-p G = -1, +2, VO = 0.2 V p-p G = 1, VO = 1 V p-p G = 1, VO = 0.2 V p-p G = 1, VO = 1 V Step, RL = 2 k G = 2, VO = 1.5 V Step, RL = 2 k G = 2, VO = 1 V Step fC = 5 MHz, VO = 2 V p-p, RL = 1 k fC = 20 MHz, VO = 2 V p-p, RL = 1 k f = 5 MHz, G = 2 f = 100 kHz f = 100 kHz Min 150 60 Typ 300 115 250 30 280 230 40 -60 -44 -90 8.5 1.2 1 2 3.5 3.5 4 0.3 70 90 13 1 -0.2 to +1.2 80 0.3 0.3 0.1 to 2.87 0.1 to 2.9 25 25 300 40 300 0.8 1.2 2.7 6.8 0.4 72 80 3 9 2.85 2.90 6 6 8.5 8.5 4.5 Max Unit MHz MHz MHz MHz V/s V/s ns dBc dBc dBc nV/Hz pA/Hz mV mV V/C A A A dB dB M pF V dB V V mA pF pF ns ns V V V mA mA dB
190 180
NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage
TMIN to TMAX Input Offset Voltage Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Capacitive Load Drive, VOUT = 0.8 V POWER-DOWN DISABLE Turn-On Time Turn-Off Time DISABLE Voltage--Off DISABLE Voltage--On POWER SUPPLY Operating Range Quiescent Current per Amplifier Supply Current when Disabled (AD8063 Only) Power Supply Rejection Ratio
Specifications subject to change without notice.
VO = 0.5 V to 2.5 V, RL = 150 VO = 0.5 V to 2.5 V, RL = 2 k
66 74
VCM = -0.2 V to +1.2 V RL = 150 RL = 2 k VO = 0.5 V to 2.5 V 30% Overshoot, G = 1, RS = 0 , G = 2, RS = 4.7
REV. C
-3-
AD8061/AD8062/AD8063-SPECIFICATIONS unless otherwise noted)
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Conditions G = 1, VO = 0.2 V p-p G = -1, +2, VO = 0.2 V p-p G = 1, VO = 1 V p-p G = 1, VO = 0.2 V p-p, VO DC = 1 V G = 1, VO = 0.7 V Step, RL = 2 k G = 2, VO = 1.5 V Step, RL = 2 k G = 2, VO = 1 V Step fC = 5 MHz, VO = 2 V p-p, RL = 1 k fC = 20 MHz, VO = 2 V p-p, RL = 1 k f = 5 MHz, G = 2 f = 100 kHz f = 100 kHz Min 150 60 Typ 300 115 230 30 150 130 40 -60 -44 -90 8.5 1.2 1 2 3.5 3.5 4 0.3 70 90
(TA = 25 C, VS = 2.7 V, RL = 1 k , VO = 1 V,
Max Unit MHz MHz MHz MHz V/s V/s ns dBc dBc dBc nV/Hz pA/Hz 6 6 mV mV V/C A A A dB dB M pF V dB 2.55 2.6 V V mA pF pF ns ns V V 8 8.5 V mA mA dB
Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% NOISE/DISTORTION PERFORMANCE Total Harmonic Distortion Crosstalk, Output to Output Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage
110 95
TMIN to TMAX Input Offset Voltage Drift Input Bias Current TMIN to TMAX Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Common-Mode Voltage Range Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Capacitive Load Drive, VOUT = 0.8 V POWER-DOWN DISABLE Turn-On Time Turn-Off Time DISABLE Voltage--Off DISABLE Voltage--On POWER SUPPLY Operating Range Quiescent Current per Amplifier Supply Current when Disabled (AD8063 Only) Power Supply Rejection Ratio
Specifications subject to change without notice.
8.5 4.5
VO = 0.5 V to 2.2 V, R L = 150 VO = 0.5 V to 2.2 V, R L = 2 k
63 74
VCM = -0.2 V to +0.9 V RL = 150 RL = 2 k VO = 0.5 V to 2.2 V 30% Overshoot: G = 1, R S = 0 , G = 2, RS = 4.7 0.3 0.25
13 1 -0.2 to +0.9 80 0.1 to 2.55 0.1 to 2.6 25 25
300 40 300 0.5 0.9 2.7 6.8 0.4 80
-4-
REV. C
AD8061/AD8062/AD8063
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V Internal Power Dissipation2 Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 0.8 W SOT-23-5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W SOT-23-6 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W Input Voltage (Common-Mode) (-VS - 0.2 V) to (+VS - 1.8 V) Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range R, RM, SOT-23-5, SOT-23-6 . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C Operating Temperature Range . . . . . . . . . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: 8-Lead SOIC Package: JA = 160C/W; JC = 56C/W 5-Lead SOT-23-5 Package: JA = 240C/W; JC = 92C/W 6-Lead SOT-23-6 Package: JA = 230C/W; JC = 92C/W 8-Lead SOIC Package: JA = 200C/W; JC = 44C/W.
The maximum power that can be safely dissipated by the AD806x is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD806x is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
2.0
MAXIMUM POWER DISSIPATION - Watts
8-LEAD SOIC PACKAGE 1.5
TJ = 150 C
1.0
0.5
SOIC SOT-23-5, -6
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 AMBIENT TEMPERATURE - C
70
80
90
Figure 2. Plot of Maximum Power Dissipation vs. Temperature for AD8061/AD8062/AD8063
ORDERING GUIDE
Model AD8061AR AD8061AR-REEL AD8061AR-REEL7 AD8061ART-REEL AD8061ART-REEL7 AD8062AR AD8062AR-REEL AD8062AR-REEL7 AD8062ARM AD8062ARM-REEL AD8062ARM-REEL7 AD8063AR AD8063AR-REEL AD8063AR-REEL7 AD8063ART-REEL AD8063ART-REEL7
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 5-Lead SOT-23 5-Lead SOT-23 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 6-Lead SOT-23 6-Lead SOT-23
Package Option SO-8 13-Inch Tape and Reel 7-Inch Tape and Reel RT-5, 13-Inch Tape and Reel RT-5, 7-Inch Tape and Reel SO-8 13-Inch Tape and Reel 7-Inch Tape and Reel RM-8 13-Inch Tape and Reel 7-Inch Tape and Reel SO-8 13-Inch Tape and Reel 7-Inch Tape and Reel RT-6, 13-Inch Tape and Reel RT-6, 7-Inch Tape and Reel
Branding Information
HGA HGA
HCA HCA HCA
HHA HHA
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8061/AD8062/AD8063 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
-5-
AD8061/AD8062/AD8063-Typical Performance Characteristics
1.2
3
VOLTAGE DIFFERENTIAL FROM VS
1.0
+VOUT @ +85 C +VOUT @ +25 C
G=1 0
0.8
NORMALIZED GAIN - dB
-3
G=2
0.6
+VOUT @ -40 C -VOUT @ -40 C
-6 G=5 -9 VO = 0.2V p-p RL = 1k VBIAS = 1V
0.4
0.2 -VOUT @ +25 C 0 0 10 20 30 40 50 60 LOAD CURRENT - mA
-VOUT @ +85 C
-12
70 80 90
1
10 100 FREQUENCY - MHz
1000
TPC 1. Output Saturation Voltage vs. Load Current
TPC 4. Small Signal Frequency Response
18 16
POWER SUPPLY CURRENT - mA
3
AD8062
0
VO = 1.0V p-p RL = 1k VBIAS = 1V
G=1
14
NORMALIZED GAIN - dB
G=2 -3
12 10 AD8061 8 6 4 2 0 2 3 4 5 6 SINGLE POWER SUPPLY - Voltage 7 8
-6
G=5
-9
-12 1 10 100 FREQUENCY - MHz 1000
TPC 2. ISUPPLY vs. VSUPPLY
TPC 5. Large Signal Frequency Response
3 RF = 50 0
3 VS = 5V VO = 0.2V p-p RL = 1k VBIAS = 1V G = -1 -3 RF -6 OUT IN 50 -9
VBIAS
0
RF = 0
NORMALIZED GAIN - dB
NORMALIZED GAIN - dB
-3
VO = 0.2V p-p RL = 1k VBIAS = 1V RF
G = -5 G = -2
-6 OUT IN 50 -9 RL
RL
VBIAS -12
10 100 FREQUENCY - MHz 1000
-12 1
1
10 100 FREQUENCY - MHz
1000
TPC 3. Small Signal Response, RF = 0 , 50
TPC 6. Small Signal Frequency Response
-6-
REV. C
AD8061/AD8062/AD8063
3 VS = 5V VO = 1V p-p RL = 1k VBIAS = 1V G = -1 -3 G = -2 -6 G = -5 -9 0 -10 HARMONIC DISTORTION - dBc -20 -30 2ND @ 1MHz -40 -50 -60 -70 -80 -90 -12 1 10 100 FREQUENCY - MHz 1000 -100 0.5 2ND @ 10MHz 1.0 3RD @ 1MHz 3.0 3.5 3RD @ 10MHz VS = 5V RL = 1k G=1 0
NORMALIZED GAIN - dB
1.5 2.0 2.5 INPUT SIGNAL BIAS - V
TPC 7. Large Signal Frequency Response
TPC 10. Harmonic Distortion for a 1 V p-p Signal vs. Input Signal DC Bias
0.1 VS = 2.7V 0
-40
VO = 0.2V p-p RL = 1k VBIAS = 1V G=1
+5V
604
10 F + 0.1 F
-50
1k
NORMALIZED GAIN - dB
-60
DISTORTION - dB
-0.1 VS = 5.0V -0.2 VS = 3.0V
50
1M 0.1 F + - INPUT
52.3 +1.25Vdc 1k (RLOAD)
-70 -80 -90
2ND H
-0.3
-0.4
-100 3RD H
1 10 100 FREQUENCY - MHz 1000
-0.5
-110 0.01
0.1 1 10 FREQUENCY - MHz, START = 10kHz, STOP = 30MHz
50
TPC 8. 0.1 dB Flatness
TPC 11. Harmonic Distortion for a 1 V p-p Output Signal vs. Input Signal DC Bias
80
200 150
-30 -40 -50 PHASE - Degrees 2ND 3RD 10MHz
60 OPEN-LOOP GAIN - dB
SERIES 1
100 50
VS = 5V RL = 1k G=5 VO = 1V p-p
DISTORTION - dB
40 SERIES 2 20
-60 -70 -80 -90 -100 -110 -120 0 1 2 3 OUTPUT SIGNAL DC BIAS - V 4 5 3RD 2ND 3RD 5MHz 1MHz 2ND
0 -50 -100
0
-150 -200 -250
-20
-40 0.01
0.1
1.0
10
100
-300 1000
FREQUENCY - MHz
TPC 9. AD8062 Open-Loop Gain and Phase vs. Frequency, VS = 5 V, RL = 1 k
TPC 12. Harmonic Distortion vs. Output Signal DC Bias
REV. C
-7-
AD8061/AD8062/AD8063
DIFFERENTIAL GAIN - % -40 -50 VS = 5V RF = RL = 1k G=2 2ND @ 10MHz
0.01 0.00 -0.01 -0.02 -0.04 -0.06 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
-60 DISTORTION - dB
50 1k
5V
+ 10 F
0.1 F
-70 -80 -90
1k
50 1k
1M INPUT TO 3589A
2ND @ 2MHz
2ND @ 500kHz 3RD @ 2MHz
DIFFERENTIAL PHASE - Degrees
0.02 0.00 -0.02 -0.04 -0.06 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
-100 3RD @ 500kHz -110 1.0 1.5 2.0 3.5 2.5 3.0 RTO OUTPUT - V p-p 4.0 4.5
TPC 13. Harmonic Distortion vs. Output Signal Amplitude
TPC 16. Differential Gain and Phase Error, G = 2, NTSC Input Signal, RL = 1 k, VS = 5 V
-30 -40 -50
DISTORTION - dB
VS = 5V RI = RL = 1k VO = 2V p-p G = +2 S1 3RD HARMONIC/ DUAL 2.5V SUPPLY S1 2ND HARMONIC/ DUAL 2.5V SUPPLY S1 2ND HARMONIC/ SINGLE +5V SUPPLY
DIFFERENTIAL GAIN - %
0.010 0.005 0.000 -0.005 -0.010 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
-60 -70 -80 -90 -100 -110 0.01
DIFFERENTIAL PHASE - Degrees
S1 3RD HARMONIC/ SINGLE +5V SUPPLY 0.1 1 10 FREQUENCY - MHz, START = 10kHz, STOP = 30MHz
0.04 0.03 0.02 0.01 0.00 -0.01 -0.02 1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
TPC 14. Harmonic Distortion vs. Frequency
TPC 17. Differential Gain and Phase Error, G = 2, NTSC Input Signal, RL = 150 , VS = 5 V
1000 900 800 VS = 5V RL = 1k G=1 FALLING EDGE
1.0 0.9 0.8
VS = 5V RL = 1k G=1
OUTPUT VOLTAGE - V
SLEW RATE - V/ s
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.10 0.20 TIME - 0.30 s 0.40 0.50
700 RISING EDGE 600 500 400 300 200 100 0 1.0 1.5 2.0 2.5 OUTPUT STEP AMPLITUDE - V 3.0
TPC 15. 400 mV Pulse Response
TPC 18. Slew Rate vs. Output Step Amplitude
-8-
REV. C
AD8061/AD8062/AD8063
1400 FALLING EDGE VS = 4V
2.5V VS = 2.5V G=1 RL = 1k
1200 1000
SLEW RATE - V/ s
VIN
FALLING EDGE VS = +5V
VOLTS
VOUT
800
600 400 200
RISING EDGE VS = 4V RISING EDGE VS = +5V
0.0V
500mV/DIV
0 0 0.5 1.0 2.5 1.5 2.0 OUTPUT STEP - V 3.0 3.5 4.0
0 20 40 60 80 100 120 TIME - ns 140 160 180 200
TPC 19. Slew Rate vs. Output Step Amplitude, G = 2, RL = 1 k, VS = 5 V
TPC 22. Input Overload Recovery, Input Step = 0 V to 2 V
1000 VS = 5V RL = 1k
VOLTAGE NOISE - nV/ Hz
VOUT VS = 2.5V G=5 RL = 1k
100
VOLTS
2.5V
1.0V
VIN
10
0.0V 500mV/DIV
1 10
100
1k
10k 100k FREQUENCY - Hz
1M
10M
0
20
40
60
80
100 120 TIME - ns
140
160
180
200
TPC 20. Voltage Noise vs. Frequency
TPC 23. Output Overload Recovery, Input Step = 0 V to 1 V
100 VS = 5V RL = 1k CURRENT NOISE - pA/ Hz
0 -10 -20 -30
CMRR - dB
VCM = 0.2V p-p RL = 100 VS = 2.5V
SIDE 2
10
SIDE 1 -40 -50 -60 -70 -80 -90 VIN 200mV p-p 604 154 57.6 154 604 50
1
0 10
100
1k 10k 100k FREQUENCY - Hz
1M
10M
-100 0.01
0.1
1 10 FREQUENCY - MHz
100
500
TPC 21. Current Noise vs. Frequency
TPC 24. CMRR vs. Frequency
REV. C
-9-
AD8061/AD8062/AD8063
0 -10 -20 -30 -40 -50 +PSRR -60 -70 -80
1
ISUPPLY - mA
7
VS = 0.2V p-p RL = 1k VS = 5V -PSRR
VS = 5V 6
5 4 3 2
PSRR - dB
-90 -100 0.01
0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.1
1 10 FREQUENCY - MHz
100
500
DISABLE VOLTAGE
TPC 25. PSRR vs. Frequency Delta
TPC 28. DISABLE Voltage vs. Supply Current
-20 1k
OUTPUT TO OUTPUT CROSSTALK - dB
6
1k +2.5V
5 VDISABLE
-30 -40
OUTPUT VOLTAGE - V
-50 -60 -70
IN 50 -2.5V
OUT 1k
VS = 5V G=2 fIN = 10MHz @ 1.3VBIAS RL = 100
4 3 2 1 0 -1 0
INPUT = SIDE 2 -80 -90 -100 -110 -120 0.01 0.1
INPUT = SIDE 1
VS = 5V VIN = 400mV rms RL = 1k G=2
VOUT
1 10 FREQUENCY - MHz
100
500
0.4
0.8 TIME -
1.2 s
1.6
2.0
TPC 26. AD8062 Crosstalk, VOUT = 2.0 V p-p, RL = 1 k, G = 2, VS = 5 V
TPC 29. DISABLE Function, Voltage = 0 V to 5 V
0 -10 -20 DISABLED ISOLATION - dB -30 -40 -50 -60 -70 -80 -90 1 10 100 FREQUENCY - MHz 1000 VS = 5V VO = 0.2V p-p RL = 1k VBIAS = 1V
1000 VS = 5V VO = 0.2V p-p RL = 1k VBIAS = 1V
100
IMPEDANCE -
10
1
0.1
0.01 0.1
1
10 FREQUENCY - MHz
100
1000
TPC 27. Disabled Output Isolation Frequency Response
TPC 30. Output Impedance vs. Frequency, VOUT = 0.2 V p-p, RL = 1 k, VS = 5 V
-10-
REV. C
AD8061/AD8062/AD8063
VS = 5V RL = 1k
VS = 5V G=2 RL = 1k VIN = 1V p-p 3.5V
SETTLING TIME TO 0.1%
+0.1%
-0.1% 1k 1k
2.5V
1.5V
RL = 1k
50 t=0 20ns/DIV
500mV/DIV 0 10 20 30 40 50 60 TIME - ns 70 80 90 100
TPC 31. Output Settling Time to 0.1%
TPC 34. 1 V Step Response
50 45 40
SETTLING TIME - ns
FALLING EDGE 2.6V
VS = 5V G=2 RL = 1k VIN = 100mV
35 RISING EDGE 30 2.5V 25 20 15 10 5 0 0.5 1 1.5 OUTPUT VOLTAGE STEP 2 VS = 5V RL = 1k G=1 2.4V
20mV/DIV 2.5 0 10 20 30 40 50 60 TIME - ns 70 80 90 100
TPC 32. Settling Time vs. VOUT
TPC 35. 100 mV Step Response
VS = 5V G = -1 RF = 1k RL = 1k 4.86
VS = 5V G=2 RF = RL = 1k VIN = 4V p-p
2.43
0.0V
0.0V
1V
2s
2 s/DIV
1V/DIV
TPC 33. Output Swing
TPC 36. Output Rail-to-Rail Swing
REV. C
-11-
AD8061/AD8062/AD8063
VS = 5V G=1 RL = 1k 2.6V
2.5V
The input stage will be the headroom limit for signals when the amplifier is used in a gain of 1 for signals approaching the positive rail. Figure 3 shows a typical offset voltage versus input common-mode voltage for the AD806x amplifier on a 5 V supply. Accurate dc performance is maintained from about 200 mV below the minus supply to within 1.8 V of the positive supply. For high-speed signals, however, there are other considerations. Figure 4 shows -3 dB bandwidth versus dc input
-0.4 -0.8
2.4V
50mV/DIV 0 5 10 15 20 25 30 TIME - ns 35 40 45 50
VOS - mV
-1.2 -1.6 -2.0 -2.4 -2.8
VS = 5V G=2 RL = RF = 1k VIN = 2V p-p
TPC 37. 200 mV Step Response
-3.2 -3.6 -4.0 -0.5
4.5V
0
0.5
1.0
1.5 2.0 VCM - V
2.5
3.0
3.5
4.0
2.5V
Figure 3. VOS vs. Common-Mode Voltage, VS = 5 V
2
0.5V
0
1V/DIV 0 5 10 15 20
VCM = 3.0
25 30 TIME - ns 35 40 45 50
VCM = 3.1
GAIN - dB
-2
VCM = 3.2 VCM = 3.3 VCM = 3.4
TPC 38. 2 V Step Response
CIRCUIT DESCRIPTION
-4
The AD8061/AD8062/AD8063 family are very high-speed voltage feedback op amps. The high slew rate input stage is a true single-supply topology, capable of sensing signals at or below the minus supply rail. The rail-to-rail output stage can pull within 30 mV of either supply rail when driving light loads and within 0.3 V when driving 150 . High-speed performance is maintained at supply voltages as low as 2.7 V.
Headroom Considerations
-6
-8 0.1
1
10 100 FREQUENCY - MHz
1000
10000
These amplifiers are designed for use in low-voltage systems. To obtain optimum performance, it is useful to understand the behavior of the amplifier as input and output signals approach the amplifier's headroom limits. The AD806x's input common-mode voltage range extends from the negative supply voltage (actually 200 mV below this), or "ground" for single supply operation, to within 1.8 V of the positive supply voltage. Thus, at a gain of 2, the AD806x can provide full "rail-to-rail" output swing for supply voltage as low as 3.6 V, assuming the input signal swing from -VS (or ground) to +VS/2. At a gain of 3, the AD806x can provide a rail-to-rail output range down to 2.7 V total supply voltage. Exceeding the headroom limit is not a concern for any inverting gain on any supply voltage, as long as the reference voltage at the amplifier's positive input lies within the amplifier's input common-mode range.
Figure 4. Unity Gain Follower Bandwidth vs. Input Common Mode, VS = 5 V
voltage for a unity gain follower. As the common-mode voltage approaches the positive supply, the amplifier holds together well, but the bandwidth begins to drop at 1.9 V within +VS. This can manifest itself in increased distortion or settling time. TPC 10 plots the distortion of a 1 V p-p signal with the AD806x amplifier used as a follower on a 5 V supply versus signal commonmode voltage. Distortion performance is maintained until the input signal center voltage gets beyond 2.5 V, as the peak of the input sine wave begins to run into the upper common-mode voltage limit. Higher frequency signals require more headroom than the lower frequencies to maintain distortion performance. Figure 5 illustrates how the rising edge settling time for the amplifier configured as a unity gain follower stretches out as the top of a 1 V step input approaches and exceeds the specified input common-mode voltage limit.
-12-
REV. C
AD8061/AD8062/AD8063
For signals approaching the minus supply and inverting gain and high positive gain configurations, the headroom limit will be the output stage. The AD806x amplifiers use a common emitter style output stage. This output stage maximizes the available output range, limited by the saturation voltage of the output transistors. The saturation voltage increases with the drive current the output transistor is required to supply, due to the output transistors' collector resistance. The saturation voltage can be estimated using the equation VSAT = 25 mV + IO x 8 , where IO is the output current, and 8 is a typical value for the output transistors' collector resistance.
3.6 3.4 3.2 OUTPUT VOLTAGE - V 3.0 2V TO 3V STEP 2.8 2.6 2.4 2.4V TO 3.4V STEP 2.2 2.0 0 4 8 12 16 20 TIME - ns 24 28 32 2.1V TO 3.1V STEP 2.2V TO 3.2V STEP 2.3V TO 3.3V STEP
3.7 3.5
OUTPUT VOLTAGE - V
3.3 3.1 2.9 2.7 2.5 2.3 2.1 0 VOLTAGE STEP FROM 2.4V TO 3.6V VOLTAGE STEP FROM 2.4V TO 3.8V, 4V AND 5V VOLTAGE STEP FROM 2.4V TO 3.4V
100
200
300 400 TIME - ns
500
600
Figure 6. Pulse Response for G = 1 Follower, Input Step Overloading the Input Stage
Output
Output overload recovery is typically within 40 ns after the amplifier's input is brought to a nonoverloading value. Figure 7 shows output recovery transients for the amplifier recovering from a saturated output from the top and bottom supplies to a point at midsupply.
5.0 4.6 OUTPUT VOLTAGE 5V TO 2.5V OUTPUT VOLTAGE 0V TO 2.5V INPUT VOLTAGE EDGES R R VIN 2.5V 5V
Figure 5. Output Rising Edge for 1 V Step at Input Headroom Limits, G = 1, VS = 5 V, 0 V
INPUT AND OUTPUT VOLTAGE - V
4.2 3.8 3.4 3.0 2.6 2.2 1.8 1.4 1.0 0.60 0.20
As the saturation point of the output stage is approached, the output signal will show increasing amounts of compression and clipping. As in the input headroom case, the higher frequency signals require a bit more headroom than the lower frequency signals. TPCs 11, 12, and 13 illustrate the point, plotting typical distortion versus output amplitude and bias for gains of 2 and 5.
Overload Behavior and Recovery Input
VO
The specified input common-mode voltage of the AD806x is -200 mV below the negative supply to within 1.8 V of the positive supply. Exceeding the top limit results in lower bandwidth and increased settling time as seen in Figures 4 and 5. Pushing the input voltage of a unity gain follower beyond 1.6 V within the positive supply leads to the behavior shown in Figure 6--an increasing amount of output error as well as much increased settling time. Recovery time from input voltages 1.6 V or closer to the positive supply is about 35 ns, which is limited by the settling artifacts caused by transistors in the input stage coming out of saturation. The AD806x family does not exhibit phase reversal, even for input voltages beyond the voltage supply rails. Going more than 0.6 V beyond the power supplies will turn on protection diodes at the input stage, which will greatly increase the device's current draw.
-0.20 0 10 20 30 40 TIME - ns 50 60 70
Figure 7. Overload Recovery, G = -1, VS = 5 V
CAPACITIVE LOAD DRIVE
The AD806x family is optimized for bandwidth and speed, not for driving capacitive loads. Output capacitance will create a pole in the amplifier's feedback path, leading to excessive peaking and potential oscillation. If dealing with load capacitance is a requirement of the application, the two strategies to consider are (1) using a small resistor in series with the amplifier's output and the load capacitance and (2) reducing the bandwidth of the amplifier's feedback loop by increasing the overall noise gain.
REV. C
-13-
AD8061/AD8062/AD8063
Figure 8 shows a unity gain follower using the series resistor strategy. The resistor isolates the output from the capacitance and, more importantly, creates a zero in the feedback path that compensates for the pole created by the output capacitance.
BOARD LAYOUT CONSIDERATIONS
Maintaining the high-speed performance of the AD806x family requires the use of high-speed board layout techniques and low parasitic components. The PCB should have a ground plane covering unused portions of the component side of the board to provide a low impedance path. The ground plane should be removed near the package to reduce parasitic capacitance. Proper bypassing is critical. A ceramic 0.1 F chip capacitor should be used to bypass both supplies, and be located within 3 mm of each power pin. An additional 4.7 F to 10 F tantalum electrolytic capacitor should be connected in parallel to provide charge for fast, large signal changes at the output. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be located close to the inverting input pin. The value of the feedback resistor may come into play--for instance, 1 k interacting with 1 pF of parasitic capacitance creates a pole at 159 MHz. Stripline design techniques should be used for signal traces longer than 25 mm. These should be designed with either 50 or 75 characteristic impedance and be properly terminated at each end.
APPLICATIONS Single Supply Sync Stripper
AD8061
VIN
RSERIES VO CLOAD
Figure 8. Series Resistor Isolating Capacitive Load
Voltage feedback amplifiers like those in AD806x family will be able to drive more capacitive load without excessive peaking when used in higher-gain configurations. This is because the increased noise gain reduces the bandwidth of the overall feedback loop. Figure 9 plots the capacitance that produces 30% overshoot versus noise gain for a typical amplifier.
10000
CAPACITIVE LOAD - pF
RS = 4.7 1000
RS = 0 100
10 1
2
3 CLOSED-LOOP GAIN
4
5
When a video signal contains synchronization pulses, it is sometimes desirable to remove them prior to performing certain operations. In the case of A-to-D conversion, the sync pulses will consume some of the dynamic range, so removing them will increase the converter's available dynamic range for the video information. Figure 11 shows a basic circuit for creating a sync stripper using the AD8061 powered by a single supply. When the negative supply is at ground potential, the lowest potential to which the output can go is ground. This feature is exploited to create a waveform whose lowest amplitude is the black level of the video and does not include the sync level.
3V
Figure 9. Capacitive Load vs. Closed-Loop Gain
DISABLE OPERATION
The internal circuit for the AD8063 disable function is shown in Figure 10. When the DISABLE node is pulled below 2 V from the positive supply, the supply current will decrease from typically 6.5 mA to under 400 A, and the AD8063 output will enter a high impedance state. If the DISABLE node is not connected, and thus is allowed to float, the AD8063 will stay biased at full power.
VCC
VIDEO IN 75
3 2
7 AD8061 4
0.1 F 6 RF 1k
10 F 75 VIDEO OUT 75
2V DISABLE TO AMPLIFIER BIAS
RG 1k
PIN NUMBERS ARE FOR 8-PIN PACKAGE
Figure 11. Single 3 V Sync Stripper Using AD8061
VEE
Figure 10. Disable Circuit of the AD8063
TPC 28 shows AD8063 supply current versus DISABLE voltage. TPC 29 plots the output seen when the AD8063 input is driven with a 10 MHz sine wave, and the DISABLE is toggled from 0 V to 5 V, illustrating the part's turn-on and turn-off time. TPC 27 shows the input/output isolation response with the AD8063 shut off.
In this case, the input video signal has its black level at ground, so it comes out at ground at the input. Since the sync level is below the black level, it will not show up at the output. However, all of the active video portion of the waveform will be amplified by a gain of two and then be normalized to unity gain by the back-terminated transmission line. Figure 12 is an oscilloscope plot of the input and output waveforms.
-14-
REV. C
AD8061/AD8062/AD8063
RGB Amplifier
1 INPUT
2 OUTPUT
500mV
10 s
Most RGB graphics signals are created by video-DAC outputs that drive a current through a resistor to ground. At the video black level, the current goes to zero, and thus the voltage of the video is also zero. Before the availability of high-speed rail-torail op amps, it was essential that an amplifier have a negative supply to amplify such a signal. Such an amplifier is necessary if one wants to drive a second monitor with from the same DAC outputs. However, high-speed, rail-to-rail output amplifiers like the AD8061 and AD8062 can accept ground level input signals and output ground level signals and thus be used as RGB signal amplifiers. A combination of the AD8061 (single) and AD8062 (dual) can amplify the three video channels of an RGB system. Figure 13 shows a circuit that performs this function.
Multiplexer
Figure 12. Input and Output Waveforms for a Single Supply Video Sync Stripper Using an AD8061
Some video signals with sync are derived from single supply devices, such as video DACs. These signals can contain sync, but the whole waveform is positive, and the black level is not at ground but at some positive voltage. The circuit can be modified to provide the sync stripping function for such a waveform. Instead of connecting RG to ground, it should be connected to a dc voltage that is two times the black level of the input signal. The gain from the +input to the output is two, which means that the black level will be amplified by two to the output. However, the gain through RG is -unity to the output. It will take a dc level of twice the input black level to shift the black level to ground at the output. When this occurs, the sync will be stripped, and the active video will be passed as in the ground referenced case.
RED DAC GREEN DAC BLUE DAC
The AD8063 has a disable pin that can be used to power down the amplifier to save power, or can be used to create a mux circuit. If two (or more) AD8063 outputs are connected together and only one is enabled, then only the signal of the enabled amplifier will appear at the output. This configuration can be used to select from various input-signal sources. Additionally, the same input signal can be applied to different gain stages or differently tuned filters to make a gain-step amplifier or a selectablefrequency amplifier. Figure 14 shows a schematic of two AD8063s used to create a mux that selects between two inputs. One of these is a 1 V p-p, 3 MHz sine wave and the other is a 2 V p-p, 1 MHz sine wave.
+4V
75
75 MONITOR #1
75
75
0.1 F
75
10 F
75
1k 3V
1V P-P 3MHz
TIME BASE OUT
49.9
AD8063
1
0.1 F -4V 1k
10 F
1k
2 3
7
0.1 F 6
10 F
1k
75 RED 75 4 1k
49.9 +4V 49.9 0.1 F 1 10 F
VOUT
AD8061
3V 0.1 F 8 10 F
MONITOR #2
2V P-P 1MHz
49.9 TIME BASE IN
AD8063
0.1 F -4V
10 F
1k
2 3 5 AD8062 1
1k
75 GREEN 75
1k HCO4 SELECT
1k 6
AD8062
7
75
BLUE 75
Figure 14. Two-to-One Multiplexer Using Two AD8063s
1k
4
Figure 13. RGB Cable Driver Using AD8061 and AD8062
REV. C
-15-
AD8061/AD8062/AD8063
The SELECT signal and the output waveforms for this circuit are shown in Figure 15. For synchronization clarity, two different frequency synthesizers whose time bases are locked to each other generate the signals.
2s OUTPUT
1V
2V
Figure 15. AD8063 Mux Output
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
5-Lead SOT-23-5 (RT-5)
0.1220 (3.100) 0.1063 (2.700)
8-Lead SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.0709 (1.800) 0.0590 (1.500) PIN 1
5 1 2
4 3
0.1181 (3.000) 0.0984 (2.500)
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0374 (0.950) REF 0.0748 (1.900) REF 0.0512 (1.300) 0.0354 (0.900) 0.0059 (0.150) 0.0000 (0.000) 0.0571 (1.450) 0.0354 (0.900) 0.0197 (0.500) 0.0118 (0.300) SEATING PLANE 10 0
0.0500 (1.27) BSC
0.0079 (0.200) 0.0035 (0.090)
0.0196 (0.50) 0.0099 (0.25) 0.0688 (1.75) 0.0532 (1.35)
45
0.0098 (0.25) 0.0040 (0.10) SEATING PLANE
0.0192 (0.49) 0.0138 (0.35)
8 0.0098 (0.25) 0 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
0.0236 (0.600) 0.0039 (0.100)
6-Lead SOT-23-6 (RT-6)
0.122 (3.10) 0.106 (2.70)
8-Lead SOIC (RM-8)
0.122 (3.10) 0.114 (2.90)
0.071 (1.80) 0.059 (1.50) PIN 1
6 1
5 2
4 3
8
5
0.118 (3.00) 0.098 (2.50)
0.122 (3.10) 0.114 (2.90)
1 4
0.193 (4.90) BSC
0.037 (0.95) BSC 0.075 (1.90) BSC 0.051 (1.30) 0.035 (0.90) 0.006 (0.15) 0.000 (0.00) 0.057 (1.45) 0.035 (0.90) 0.020 (0.50) SEATING 0.010 (0.25) PLANE 10 0.009 (0.23) 0 0.003 (0.08) 0.022 (0.55) 0.014 (0.35)
PIN 1 0.0256 (0.65) BSC 0.006 (0.15) 0.002 (0.05) 0.016 (0.40) 0.010 (0.25) 0.043 (1.10) MAX 6 0 SEATING 0.009 (0.23) PLANE 0.005 (0.13)
0.037 (0.95) 0.030 (0.75)
0.028 (0.70) 0.016 (0.40)
AD8061/AD8062/AD8063-Revision History
Location Page
Data Sheet changed from REV. B to REV. C. Replaced TPC 9 with new graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -16- REV. C
PRINTED IN U.S.A.
C01065-0-5/01(C)
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